MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 848

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Time Processor Unit 3
19.4.9
The channel priority registers (CPR1, CPR2) assign one of three priority levels to a channel or disable the
channel. See
19-18
SRESET
SRESET
Field
Addr
Field
Addr
CH[15:0]
CH[15:0]
Name
Name
MSB
MSB
Channel Priority Registers (CPRx)
0
0
CH 15
Appendix D, “TPU3 ROM
CH 7
Encoded type of host service. The host service request field selects the type of host service request for
the time function selected on a given channel. The meaning of the host service request bits depends
on the time function specified.
A host service request field cleared to 0b00 signals the host that service is completed by the
microengine on that channel. The host can request service on a channel by writing the corresponding
host service request field to one of three non-zero states. The CPU must monitor the host service
request register until the TPU3 clears the service request to 0b00 before any parameters are changed
or a new service request is issued to the channel.
Encoded channel priority levels.
channel priority encoding.
1
1
2
2
CH 14
CH 6
Figure 19-18. CPR0 — Channel Priority Register 0
Figure 19-19. CPR1 — Channel Priority Register 1
3
3
CHx[1:0]
MPC561/MPC563 Reference Manual, Rev. 1.2
00
01
10
11
Table 19-14. HSSRn Bit Descriptions
4
Table 19-15. CPRn Bit Description
4
CH 13
CH 5
Table 19-16. Channel Priorities
0x30 401C (TPU_A), 0x30 441C (TPU_B)
0x30 401E (TPU_A), 0x30 441E (TPU_B)
Functions,” for more information.
5
5
Disabled
Service
Table 19-16
Middle
High
Low
0000_0000_0000_0000
0000_0000_0000_0000
6
6
CH 12
CH 4
Description
7
Description
7
indicates the number of time slots guaranteed for each
Guaranteed Time Slots
8
8
CH 11
1 out of 7
2 out of 7
4 out of 7
CH 3
—
9
9
10
10
CH 10
CH 2
11
11
12
12
CH 9
CH 1
Freescale Semiconductor
13
13
14
14
CH 0
CH 8
LSB
LSB
15
15