MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 108

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Signal Descriptions
2-10
XTAL
EXTAL
XFC
CLKOUT
EXTCLK
ENGCLK / BUCLK
VDDSYN
VSSSYN
PULL_SEL
A_CNTX0
A_CNRX0
B_CNTX0
Signal Name
3
Table 2-1. MPC561/MPC563 Signal Descriptions (continued)
Signals
No. of
1
1
1
1
1
1
1
1
1
1
1
1
MPC561/MPC563 Reference Manual, Rev. 1.2
Type
O
O
O
O
O
O
I
I
I
I
I
I
I
XTAL
EXTAL
XFC
CLKOUT
EXTCLK
ENGCLK (2.6
V)
VDDSYN
VSSSYN
PULL_SEL
A_CNTX0
A_CNRX0
B_CNTX0
Function after
Reset
Clocks and PLL
Configuration
TouCAN
1
XTAL. This output signal is one of the connections to an
external crystal for the internal oscillator circuitry.
EXTAL. This signal is one of the connections to an external
crystal for the internal oscillator circuitry. If EXTAL is unused,
it must be grounded.
External Filter Capacitance. This input signal is the
connection for an external capacitor filter for the PLL
circuitry.
Clock Out. This output signal is the clock system frequency.
The CLKOUT drive strength can be configured to full
strength, half strength, quarter strength, or disabled. The
drive strength is configured using the COM[0:1] bits and
CQDS bits in the SCCR register in the USIU.
EXTCLK. This is the external frequency source for the
MPC561/MPC563. If EXTCLK is unused, it must be
grounded.
ENGCLK. This is the engineering clock output. Drive voltage
can be configured to 2.6 V, 5 V (with slew-rate control), or
disabled. The drive voltage is configured using the
EECLK[0:1] bits in the SCCR register in the SIU.
BUCLK. When the MPC561/MPC563 is in limp mode, it is
operating from a less precise on-chip ring oscillator to allow
the system to continue minimum functionality until the
system clock is fixed. This backup clock can be seen
externally if selected by the values of the EECLK[0:1] bits in
the SCCR register in the USIU.
VDDSYN. This is the power supply of the PLL circuitry.
VSSSYN. This is the ground reference of the PLL circuitry.
Pull Select. PULL_SEL determines whether the pull devices
on the MIOS and TPU signals are pull-ups or pull-downs.
When pull-ups are selected, the pull-ups are to 5.0 V except
the following MIOS signals will be pulled to 2.6V:
VF[0:2]/MPIO32B[0:2], VFLS[0:1]/MPIO32B[3:4], and
MDO[7:4]/MPIO32B[7:10]. When this pin is low, pull-downs
are selected.
TouCAN_A Transmit Data. This signal is the serial data
output.
TouCAN_A Receive Data. This signal is the serial data
input.
TouCAN_B Transmit Data. This signal is the serial data
output.
Description
Freescale Semiconductor