MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 620

MPC561MZP56

Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet

Specifications of MPC561MZP56

Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant

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Queued Serial Multi-Channel Module
15.2
Standard SPI features are listed below, followed by a list of the additional features offered on the QSPI:
QSPI-enhanced features are as follows:
15-2
IMB3*
Full-duplex, three-wire synchronous transfers
Half-duplex, two-wire synchronous transfers
Master or slave operation on the SPI bus
Programmable master bit rates
Programmable clock polarity and phase
End-of-transmission interrupt flag
Master-master mode fault flag
Easily interfaces to simple expansion parts (A/D converters, EEPROMS, display drivers, etc.)
Programmable Queue — up to 32 preprogrammed transfers
Programmable Peripheral Chip-Selects — four pins select up to 16 SPI chips
Wraparound Transfer Mode — for autoscanning of serial A/D (or other) peripherals, with no CPU
overhead
Programmable Transfer Length — from 8–16 bits inclusive
Key Features
Note: SBIU bus and interface to IMB3 are each 16 bits wide.
Receive and Transmit Queue
MPC561/MPC563 Reference Manual, Rev. 1.2
QSPI QUEUE RAM
Figure 15-1. QSMCM Block Diagram
QSPI
DSCI
DSCI
SBIU
SCI2
SCI1
2
7
2
Freescale Semiconductor
SCK/QGPIO6
PCS1/QGPIO1
PCS3/QGPIO3
RXD1/QGPI1
TXD2/QGPO2
MISO/QGPIO4
MOSI/QGPIO5
PCS0/SS/QGPIO0
PCS2/QGPIO2
TXD1/QGPO1
RXD2/QGPI2

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