MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 257

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

6.1.5
The bus monitor ensures that each bus cycle is terminated within a reasonable period of time. The USIU
provides a bus monitor option to monitor internal to external bus accesses on the external bus. The monitor
counts from transfer start to transfer acknowledge and from transfer acknowledge to transfer acknowledge
within bursts. If the monitor times out, transfer error acknowledge (TEA) is asserted internally by the
Freescale Semiconductor
.
Hardware Bus Monitor
Flow with lower priority
masking enabled
Flow without lower priority
masking enabled
Figure 6-6. Typical Interrupt Handler Routine
Clearing in-service bit
MPC561/MPC563 Reference Manual, Rev. 1.2
Restoring the CPU
Saving the CPU
Clearing interrupt
Disabling interrupt
priority requests
Masking lower
Clearing mask
Handler body
Interrupt
Enabling
context
context
Start
source
RFI
System Configuration and Protection
6-17