MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 63

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Table
Number
i
ii
1-1
1-2
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
Freescale Semiconductor
Notational Conventions ..................................................................................................... 1-lxxxii
Acronyms and Abbreviated Terms .................................................................................... 1-lxxxii
MPC56x Family Features ......................................................................................................... 1-1
Differences Between MPC555 and MPC561/MPC563............................................................ 1-9
MPC561/MPC563 Signal Descriptions .................................................................................... 2-3
MPC561/MPC563 Signal Sharing.......................................................................................... 2-20
Reduced and Full Port Mode Pads.......................................................................................... 2-21
Full Port Only Mode Pads ...................................................................................................... 2-21
PDMCR Field Descriptions .................................................................................................... 2-22
PDMCR2 Field Description.................................................................................................... 2-24
TCNC Pad Functionalities ...................................................................................................... 2-25
PPMPAD Pad Functionalities................................................................................................. 2-25
Enhanced PCS 4 & 5 Pad Function ........................................................................................ 2-26
Enhanced PCS 6 & 7 Pad Function ........................................................................................ 2-28
MPC561/MPC563 Development Support Shared Signals ..................................................... 2-28
MPC561/MPC563 Signal Reset State .................................................................................... 2-34
RCPU Execution Units ............................................................................................................. 3-4
Supervisor-Level SPRs ............................................................................................................. 3-9
Development Support SPRs.................................................................................................... 3-11
FPSCR Bit Categories ............................................................................................................ 3-13
FPSCR Bit Descriptions ......................................................................................................... 3-14
Floating-Point Result Flags in FPSCR ................................................................................... 3-16
Bit Settings for CR0 Field of CR............................................................................................ 3-17
Bit Settings for CR1 Field of CR............................................................................................ 3-17
CRn Field Bit Settings for Compare Instructions ................................................................... 3-18
Integer Exception Register Bit Descriptions .......................................................................... 3-18
Machine State Register Bit Descriptions ................................................................................ 3-20
Floating-Point Exception Mode Bits ...................................................................................... 3-22
Uses of SPRG0–SPRG3 ......................................................................................................... 3-24
Processor Version Register Bit Descriptions.......................................................................... 3-25
EIE, EID, AND NRI Registers ............................................................................................... 3-25
FPECR Bit Descriptions ......................................................................................................... 3-26
Instruction Set Summary ........................................................................................................ 3-28
RCPU Exception Classes........................................................................................................ 3-35
Instruction Latency and Blockage .......................................................................................... 3-39
Floating-Point Exception Mode Encoding ............................................................................. 3-44
Enhanced PCS Functionality ................................................................................................. 2-25
MPC561/MPC563 Mode Selection Options.......................................................................... 2-29
Exception Vector Offset Table .............................................................................................. 3-36
MPC561/MPC563 Reference Manual, Rev. 1.2
Tables
Title
Number
Page
lxiii