MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 627

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

15.4.7
The QTEST register is used for factory testing of the MCU.
15.4.8
The QDSCI_ILI and QSPI_IL registers determine the interrupt level requested by the QSMCM. The two
SCI submodules (DSCI) share a 5-bit interrupt level field, ILDSCI. The QSPI uses a separate field,
ILQSPI. The level value is used to determine which interrupt is serviced first when two or more modules
or external peripherals simultaneously request an interrupt. The user can select among 32 levels. This
register can be accessed only when the CPU is in supervisor mode.
Freescale Semiconductor
SRESET
12:15
Bits
9:11
Bits
8:15
Field
Addr
2:7
0:2
3:7
0
1
8
QSMCM Test Register (QTEST)
QSMCM Interrupt Level Registers (QDSCI_IL, QSPI_IL)
MSB
0
ILDSCI
Name
STOP
SUPV
Name
FRZ1
—
—
—
—
—
—
Figure 15-5. QSM2 Dual SCI Interrupt Level Register (QDSCI_IL)
1
2
Stop enable. Refer to
0 Normal clock operation
1 Internal clocks stopped
Freeze1 bit. Refer to
0 Ignore the FREEZE signal
1 Halt the QSMCM (on transfer boundary)
Reserved
Supervisor / Unrestricted. Refer to
0 Assigned registers are unrestricted (user access allowed)
1 Assigned registers are restricted (only supervisor access allowed)
Reserved
Reserved. These bits are used for the IARB (interrupt arbitration ID) field in QSM
implementations that use hardware interrupt arbitration.
Reserved
Interrupt level of Dual SCIs
00000lowest interrupt level request (level 0)
11111highest interrupt level request (level 31)
Reserved
Table 15-4. QSMCMMCR Bit Descriptions
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 15-5. QDSCI_IL Bit Descriptions
3
4
ILDSCI
5
Section 15.4.2, “Freeze
Section 15.4.1, “Low-Power Stop
0000_0000_0000_0000
6
0x30 5004
Section 15.4.3, “Access
7
Description
Description
8
Operation.”
9
10
Operation.”
Queued Serial Multi-Channel Module
Protection.”
11
—
12
13
14
LSB
15
15-9