MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 263

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

6.1.11
When the FREEZE line is asserted, the clocks to the software watchdog, the periodic interrupt timer, the
real-time clock, the time base counter, and the decrementer can be disabled. This is controlled by the
associated bits in the control register of each timer. If programmed to stop during FREEZE assertion, the
counters maintain their values while FREEZE is asserted. The bus monitor remains enabled regardless of
this signal.
6.1.12
When the processor is set in a low-power mode (doze, sleep, or deep-sleep), the software watchdog timer
is frozen. It remains frozen and maintains its count value until the processor exits this state and resumes
executing instructions.
The periodic interrupt timer, decrementer, and time base are not affected by these low-power modes. They
continue to run at their respective frequencies. These timers are capable of generating an interrupt to bring
the MCU out of these low-power modes.
6.2
This section provides the MPC561/MPC563 memory map, register diagrams and bit descriptions of the
system configuration and protection registers.
6.2.1
The MPC561/MPC563 internal memory space can be assigned to one of eight locations.
Freescale Semiconductor
Clock
System
Memory Map and Register Definitions
Freeze Operation
Low Power Stop Operation
Memory Map
(SYPCR)
FREEZE
Disable
SWE
Clock
MPC561/MPC563 Reference Manual, Rev. 1.2
Divide By
Figure 6-10. SWT Block Diagram
2048
Service
SWSR
Logic
(SYPCR)
MUX
SWP
Reload
SWR/Decrementer
Rollover = 0
SWTC
System Configuration and Protection
16-bit
Time-out
or NMI
Reset
6-23