MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 438

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

L-Bus to U-Bus Interface (L2U)
11.3
Figure 11-1
MPC561/MPC563 bus architecture.
11-2
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Supports a default global entry for memory space not covered by other regions:
— Default access protection
— Default guarded attribute
Interrupt generated upon:
— Access violation
— Load from guarded region
— Write to read-only region
The MSR[DR] bit (data relocate) controls DMPU protection on/off operation
Programming is done using the mtspr/mfspr instructions to/from implementation-specific special
purpose registers.
No protection for accesses to the CALRAM module on the L-bus (CALRAM has its own
protection options)
L2U Block Diagram
– Access protection: user or supervisor
– Guarded attribute: speculative or non-speculative
– Enable/disable option
– Read only option
shows a block diagram of the L-bus to U-bus interface as implemented in the overall
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor