MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 800
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Modular Input/Output Subsystem (MIOS14)
17.12.4.2 Interrupt Enable Register (MIOS14ER1)
This register contains the interrupt enable bits for the submodules. Each bit corresponds to a given
submodule.
17.12.4.3 Interrupt Request Pending Register (MIOS14RPR1)
This register is a read only register that contains the interrupt pending bits for the submodules. Each bit
corresponds to a given submodule. When one of these bits is set, it means that a submodule raised its flag
and the corresponding enable was set.
As this register is read only, a write to this register has no other effect than generating a bus error if the bus
error option is selected.
17-68
SRESET
SRESET
10:15
Bits
0:4
5:6
7:9
Bits
Field
Field
0:4
5:6
Addr
Addr
EN31:27
EN24:22
EN21:16
MSB
MSB
IRP
EN
Name
31
31
IRP31:27 Pending Bits — MDASM pending bits [31:27]
0
0
—
Name
—
IRP
EN
30
30
Figure 17-40. Interrupt Request Pending Register (MIOS14RPR1)
1
1
Enable Bits — MDASM enable bits [31:27]
Reserved
Enable Bits — MMCSM enable bits [24:22]
Enable Bits — PWMSM enable bits [21:16]
Reserved
IRP
Figure 17-39. Interrupt Enable Register (MIOS14ER1)
EN
29
29
2
2
Table 17-40. MIOS14RPR1 Bit Descriptions
Table 17-39. MIOS14ER1 Bit Descriptions
IRP
MPC561/MPC563 Reference Manual, Rev. 1.2
EN
28
28
3
3
IRP
EN
27
27
4
4
5
5
0000_0000_0000_0000
—
—
6
6
0x30 6C44
0x30 6C46
Undefined
IRP
EN
24
24
7
7
Description
Description
IRP
EN
23
23
8
8
IRP
EN
22
22
9
9
IRP
EN
21
21
10
10
IRP
EN
20
20
11
11
IRP
EN
19
19
12
12
Freescale Semiconductor
IRP
EN
18
18
13
13
IRP
EN
17
17
14
14
IRP
LSB
LSB
EN
16
16
15
15
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