MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 56
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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24-73
24-74
24-75
24-76
24-77
24-78
24-79
24-80
24-81
24-82
24-83
24-84
24-85
24-86
24-87
24-88
24-89
25-1
25-2
25-3
25-4
25-5
A-1
A-2
A-3
A-4
A-5
A-6
A-7
A-8
A-9
A-10
A-11
A-12
A-13
A-14
C-1
C-2
C-3
C-4
lvi
Figure
Number
Error Message (Watchpoint Overrun) .................................................................................. 24-74
Ownership Trace Message Format ....................................................................................... 24-75
Error Message Format .......................................................................................................... 24-75
Ownership Trace Message.................................................................................................... 24-76
Error Message (Program/Data/Ownership Trace Overrun).................................................. 24-76
RCPU Development Access Multiplexing between READI and BDM Signals .................. 24-77
DSDI Message Format.......................................................................................................... 24-78
DSDO Message Format ........................................................................................................ 24-78
BDM Status Message Format ............................................................................................... 24-79
Error Message (Invalid Message) Format ............................................................................ 24-79
RCPU Development Access Flow Diagram ......................................................................... 24-81
RCPU Development Access Timing Diagram — Debug Mode Entry Out-of-Reset........... 24-83
Transmission Sequence of DSDx Data Messages ................................................................ 24-83
Error Message (Invalid Message) ......................................................................................... 24-85
DSDI Data Message (Assert Non-Maskable Breakpoint) .................................................... 24-85
DSDI Data Message (CPU Instruction — rfi) ...................................................................... 24-85
DSDO Data Message (CPU Data Out) ................................................................................. 24-86
Pin Requirement on JTAG...................................................................................................... 25-1
Test Logic Block Diagram...................................................................................................... 25-3
JTAG Mode Selection ............................................................................................................ 25-3
TAP Controller State Machine ............................................................................................... 25-4
Bypass Register..................................................................................................................... 25-31
Instruction Compression Alternatives ..................................................................................... A-3
Addressing Instructions with Compressed Address ................................................................ A-4
Compressed Target Address Generation by Direct Branches.................................................. A-5
Branch Right Segment Compression #1 .................................................................................. A-7
Branch Right Segment Compression #2 .................................................................................. A-8
Global Bypass Instruction Layout ........................................................................................... A-8
CLASS_1 Instruction Layout .................................................................................................. A-9
CLASS_2 Instruction Layout .................................................................................................. A-9
CLASS_3 Instruction Layout ................................................................................................ A-10
CLASS_4 Instruction Layout ................................................................................................ A-11
Code Compression Process.................................................................................................... A-12
Code Decompression Process ................................................................................................ A-13
I-Bus Support Control Register (ICTRL) .............................................................................. A-16
Decompressor Class Configuration Registers1 (DCCR
MPC561/MPC563 Power Distribution Diagram — 2.6 V .......................................................C-3
Power Distribution Diagram — 5 V and Analog .....................................................................C-3
Crystal Oscillator Circuit ..........................................................................................................C-4
RC Filter Example ....................................................................................................................C-5
MPC561/MPC563 Reference Manual, Rev. 1.2
Figures
Title
x
) ..................................................... A-19
Freescale Semiconductor
Number
Page
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