MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 736

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Modular Input/Output Subsystem (MIOS14)
17.2.1
A block is a group of four 16-bit registers. Each of the blocks within the MIOS14 addressing range is
assigned a block number. The first block is located at the base address of the MIOS14. The blocks are
numbered sequentially starting from 0.
17-4
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— Possible use of signal as I/O port when MDASM function is not needed
MIOS14 pulse width modulation submodule (MPWMSM):
— Output pulse width modulated (PWM) signal generation with no software involvement
— Built-in 8-bit programmable prescaler clocked by the MCPSM
— PWM period and pulse width values provided by software:
— Programmable duty cycle from 0% to 100%
— Possible interrupt generation after every period
— Software selectable output pulse polarity
— Software readable output signal status
— Possible use of signal as I/O port when PWM function is not needed
MIOS14 16-bit parallel port I/O submodule (MPIOSM):
— Up to 16 parallel I/O signals per MPIOSM
— Uses four 16-bit registers in the address space, one for data and one for direction and two
— Simple data direction register (DDR) concept for selection of signal direction
– Double-buffered for glitch-free period and pulse width changes
– Two-cycle minimum output period/pulse-width increment
– 50% duty-cycle output maximum frequency: 10 MHz
– Up to 16 bits output pulse width resolution
– Wide range of periods:
– Wide range of frequencies:
reserved
Submodule Numbering, Naming, and Addressing
(50 ns @ 40 MHz)
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16 bits of resolution: period range from 3.27 ms (with 50-ns steps) to
6.71 s (with 102.4 µs steps)
Eight bits of resolution: period range from 12.8 µs (with 50-ns steps) to
26.2 ms (with 102.4-µs steps)
Maximum output frequency at f
and divide-by-2 prescaler selection: 305 Hz (3.27 ms)
Minimum output frequency at f
and divide-by-4096 prescaler selection: 0.15 Hz (6.7 s)
Maximum output frequency at f
resolution and divide-by-2 prescaler selection: 78125 Hz (12.8 µs)
Minimum output frequency at f
and divide-by-4096 prescaler selection: 38.14 Hz (8.2 ms)
MPC561/MPC563 Reference Manual, Rev. 1.2
SYS
SYS
SYS
SYS
= 40 MHz with 16 bits of resolution
= 40 MHz with 16 bits of resolution
= 40 MHz with 8 bits of resolution
= 40 MHz with eight bits of
Freescale Semiconductor