MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1141

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Freescale Semiconductor
0x38 0000
1
2
1
0x30 7980 —
0x30 798F
0x30 7990 —
0x30 799F
0x30 79A0 —
0x30 79AF
0x30 79B0 —
0x30 79BF
0x30 79C0 —
0x30 79CF
0x30 79D0 —
0x30 79DF
0x30 79E0 —
0x30 79EF
0x30 79F0 —
0x30 79FF
0x30 7F80
0x30 7F84 —
0x30 7F8C
0x30 7F90
0x30 7F94 —
0x30 7F9C
0x30 7FA0
Address
The last word of each of the MBUFF arrays (address 0x....E) is reserved and may cause a RCPU exception if read.
See
S = Supervisor mode only, T = Test mode only
Address
Address
Table 16-3
Access
and
Access
Access
Table B-14. TouCAN A, B and C (CAN 2.0B Controller) (continued)
S
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/T
S
—
—
S
Table 16-4
1
Table B-15. UIMB (U-Bus to IMB Bus Interface)
CRAMMCR
MBUFF10_C
MBUFF11_C
MBUFF12_C
MBUFF13_C
MBUFF14_C
MBUFF15_C
MBUFF8_C
MBUFF9_C
UTSTCREG
Symbol
for message buffer definitions.
UIPEND
Symbol
Symbol
MPC561/MPC563 Reference Manual, Rev. 1.2
UMCR
Table B-16. CALRAM Control Registers
—
—
1
1
1
1
1
1
1
1
CALRAMModule Configuration Register.
See
TouCAN_C Message Buffer 8.
TouCAN_C Message Buffer 9.
TouCAN_C Message Buffer 10.
TouCAN_C Message Buffer 11.
TouCAN_C Message Buffer 12.
TouCAN_C Message Buffer 13.
TouCAN_C Message Buffer 14.
TouCAN_C Message Buffer 15.
UIMB Module Configuration Register.
See
Reserved
UIMB Test Control Register.
Reserved
Reserved
Pending Interrupt Request Register.
See
descriptions.
Table 22-3
Table 12-6
Section 12.5.3
CALRAM
for bit descriptions.
for bit descriptions.
Register
Register
Register
and
Table 12-7
for bit
Size
Size
—
—
—
—
—
—
—
—
32
32
32
32
32
Size
32
Internal Memory Map
Reset
Reset
Reset
U
U
U
U
U
U
U
U
H
H
H
H
H
S
B-31