MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 933

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

23.2.3
There are two 16-bit watchpoint counters. Each counter is able to count one of the instruction watchpoints
or one of the load/store watchpoints. Both generate the corresponding breakpoint when they reach ZERO.
When working in the masked mode, the counters do not count watchpoints detected when MSR[RI] = 0.
See
The counters value when counting watchpoints programmed on the actual instructions that alter the
counters, are not predictable. Reading values from the counters when they are active, must be
synchronized by inserting a sync instruction before the actual read is performed.
When programmed to count load/store watchpoints, the last instruction which decrements the counter to
ZERO is treated like any other load/store breakpoint in the sense that it is executed and the machine
branches to the breakpoint exception routine AFTER it executes this instruction. Therefore, the value of
the counter inside the breakpoint exception routine equals ZERO.
23.2.3.1
The trap enable bits can be programmed by regular software (only if MSR[PR] = 0) using the mtspr
instruction or “on the fly” using the special development port interface. For more information refer to
section
The value used by the breakpoints generation logic is the bit wise OR of the software trap enable bits, (the
bits written using the mtspr) and the development port trap enable bits (the bits serially shifted using the
development port).
All bits, the software trap enable bits and the development port trap enable bits, can be read from ICTRL
and the LCTRL2 using mfspr. For the exact bits placement refer to
Control Register
23.3
When debugging an existing system, it is sometimes desirable to be able to do so without the need to insert
any changes in the existing system. In some cases it is not desired, or even impossible, to add load to the
lines connected to the existing system. The development system interface of the CPU supports such a
configuration.
The development system interface of the CPU uses a dedicated serial port (the development port) and,
therefore, does not need any of the regular system interfaces. Controlling the activity of the system from
the development port is done when the CPU is in the debug mode. The development port is a relatively
Freescale Semiconductor
Section 23.2.1.4, “Context Dependent
Section 23.4.6.5, “Development Port Serial Communications — Trap Enable
Development System Interface
Watchpoint Counters
Trap Enable Programming
When programmed to count instruction watchpoints, the last instruction
which decrements the counter to ZERO is treated like any other instruction
breakpoint in the sense that it is not executed and the machine branches to
the breakpoint exception routine BEFORE it executes this instruction. As a
side effect of this behavior, the value of the counter inside the breakpoint
exception routine equals ONE and not ZERO as might be expected.
2” and to
Section 23.6.10, “L-Bus Support Control Register
MPC561/MPC563 Reference Manual, Rev. 1.2
Filter.”
NOTE
Section 23.6.10, “L-Bus Support
2.”
Mode.”
Development Support
23-19