MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 270

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

System Configuration and Protection
6-30
1
HRESET
HRESET ID16
The reset value is a reset configuration word value, extracted from the indicated internal data bus line. Refer to
“Hard Reset Configuration Word
19:20
23:24
Field
Field PRPM SLVM
Addr
Bits
0:15
16
17
18
21
22
25
MSB
16
0
PRPM
Name
SUPU
RESV
SLVM
INST
SIZE
1
—
—
—
17
0
1
Reserved
Peripheral mode. In this mode, the internal RCPU core is shut off and an alternative master on
the external bus can access any internal slave module. The reset value of this bit is determined
by the reset configuration word bit 16. The bit can also be written by software.
0 Normal operation
1 Peripheral mode operation
Slave mode (valid only if PRPM = 0). In this mode, an alternative master on the external bus can
access any internal slave module while the internal RCPU core is fully operational. If PRPM is
set, the value of SLVM is a “don’t care.”
0 Normal operation
1 Slave mode
Reserved
Size attribute. If SIZEN = 1, the SIZE bits controls the internal bus attributes as follows:
00 Double word (8 bytes)
01 Word (4 bytes)
10 Half word (2 bytes)
11 Byte
Supervisor/user attribute. SUPU controls the supervisor/user attribute as follows:
0 Supervisor mode access permitted to all registers
1 User access permitted to registers designated “user access”
Instruction attribute. INST controls the internal bus instruction attribute as follows:
0 Instruction fetch
1 Operand or non-CPU access
Reserved
Reservation attribute. RESV controls the internal bus reservation attribute as follows:
0 Storage reservation cycle
1 Not a reservation
18
—
0
2
Figure 6-14. External Master Control Register (EMCR)
(RCW).”
19
3
SIZE
MPC561/MPC563 Reference Manual, Rev. 1.2
01
Table 6-13. EMCR Bit Descriptions
20
4
SUPU INST
21
0
5
0000_0000_0000_0000
22
1
6
0x2F C030
23
7
—
00
—
Description
24
8
RESV CONT
25
1
9
10
26
1
—
11
27
0
TRAC SIZEN
12
28
1
Freescale Semiconductor
13
29
1
Section 7.5.2,
14
30
00
—
LSB
15
31