MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 64

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

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Table
Number
Register Settings following an NMI ....................................................................................... 3-45
Machine Check Exception Processor Actions ........................................................................ 3-47
Register Settings following a Machine Check Exception ...................................................... 3-47
Register Settings following a Trace Exception....................................................................... 3-55
Register Settings following Floating-Point Assist Exceptions ............................................... 3-55
Register Settings following a Software Emulation Exception................................................ 3-56
Register Settings following an Instruction Protection Exception ........................................... 3-57
Register Settings Following a Data Protection Error Exception ............................................ 3-59
Register Settings Following a Debug Exception .................................................................... 3-60
Register Settings for Data Breakpoint Match ......................................................................... 3-60
Exception Addresses Mapping ................................................................................................. 4-9
Exception Relocation Page Offset .......................................................................................... 4-10
BBC SPRs............................................................................................................................... 4-17
Region Size Programming Possible Values............................................................................ 4-23
USIU Address Map................................................................................................................... 5-3
USIU Special-Purpose Registers .............................................................................................. 5-7
Hex Address Format for SPR Cycles ....................................................................................... 5-7
USIU Pin Multiplexing Control................................................................................................ 6-4
SGPIO Configuration ............................................................................................................... 6-7
Priority of Interrupt Sources—Regular Operation.................................................................. 6-10
Priority of Interrupt Sources—Enhanced Operation .............................................................. 6-12
Interrupt Latency Estimation for Three Typical Cases........................................................... 6-16
Decrementer Time-Out Periods .............................................................................................. 6-18
Debug Pins Configuration ...................................................................................................... 6-27
General Pins Configuration .................................................................................................... 6-27
Single-Chip Select Field Pin Configuration ........................................................................... 6-27
Settings Caused by Reset ....................................................................................................... 3-45
Register Settings following External Interrupt ...................................................................... 3-49
Register Settings for Alignment Exception ........................................................................... 3-50
Register Settings following Program Exception.................................................................... 3-52
Register Settings following a Floating-Point Unavailable Exception ................................... 3-52
Register Settings Following a Decrementer Exception ......................................................... 3-53
Register Settings following a System Call Exception ........................................................... 3-54
BBCMCR Field Descriptions ................................................................................................ 4-19
MI_RBA[0:3] Registers Bit Descriptions.............................................................................. 4-21
MI_RA[0:3] Registers Bit Descriptions ................................................................................ 4-22
MI_GRA Field Descriptions.................................................................................................. 4-24
EIBADR External Interrupt Relocation Table Base Address Register Bit Descriptions ...... 4-25
SIUMCR Bit Descriptions ..................................................................................................... 6-25
MPC561/MPC563 Reference Manual, Rev. 1.2
Tables
Title
Freescale Semiconductor
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