MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 286

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

System Configuration and Protection
6.2.2.5
6.2.2.5.1
6-46
1
If the device is configured NOT in full bus mode (i.e., SIUMCR[SC]=0b01, 0x10, or 0b11), the GPIO pins will be in input
16:23
24:31
mode and this register will reflect the state of the pins.
Reset
Reset
Bits
8:15
0:7
Field
Field
Addr
MSB
16
SGPIOD[16:23]
SGPIOD[24:31]
0
SGPIOD[8:15]
General-Purpose I/O Registers
SGPIOD[0:7]
SGPIO Data Register 1 (SGPIODT1)
Name
17
1
18
2
SGPIOD[16:23]
SIU general-purpose I/O Group D[8:15]. This 8-bit register controls the data of
SIU general-purpose I/O Group D[0:7]. This 8-bit register controls the data of
general-purpose I/O pins SGPIOD[0:7]. The direction (input or output) of this group of pins
is controlled by the GDDR0 bit in the SGPIO control register.
general-purpose I/O pins SGPIOD[8:15]. The direction (input or output) of this group of
pins is controlled by the GDDR1 bit in the SGPIO control register.
SIU general-purpose I/O Group D[16:23]. This 8-bit register controls the data of the
general-purpose I/O pins SGPIOD[16:23]. The direction (input or output) of this group of
pins is controlled by the GDDR2 bit in the SGPIO control register
SIU general-purpose I/O Group D[24:31]. This 8-bit register controls the data of the
general-purpose I/O pins SGPIOD[24:31]. The direction of SGPIOD[24:31] is controlled by
eight dedicated direction control signals SDDRD[24:31]. Each pin in this group can be
configured separately as general-purpose input or output.
SGPIOD[0:7]
19
3
Figure 6-41. SGPIO Data Register 1 (SGPIODT1)
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 6-23. SGPIODT1 Bit Descriptions
20
4
21
5
0000_0000_0000_0000
0000_0000_0000_0000
22
6
0x2F C024
23
7
24
8
Description
25
9
1
1
10
26
SGPIOD[24:31]
SGPIOD[8:15]
11
27
12
28
Freescale Semiconductor
13
29
14
30
LSB
15
31