MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 310

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Clocks and Power Control
Note that GCLK1_50, GCLK2_50, and CLKOUT can have a lower frequency than GCLK1 and GCLK2.
This is to enable the external bus operation at lower frequencies (controlled by EBDF in the SCCR).
GCLK2_50 always rises simultaneously with GCLK2. When DFNH = 0, GCLK2_50 has a 50% duty
cycle. With other values of DFNH or DFNL, the duty cycle is less than 50%. Refer to
GCLK1_50 rises simultaneously with GCLK1. When the MPC561/MPC563 is not in gear mode, the
falling edge of GCLK1_50 occurs in the middle of the high phase of GCLK2_50. EBDF determines the
division factor between GCLK1/GCLK2 and GCLK1_50/GCLK2_50.
During power-on reset, the MODCK1, MODCK2, and MODCK3 pins determine the clock source for the
PLL and the clock drivers. These pins are latched on the positive edge of PORESET. Their values must be
stable as long as this line is asserted. The configuration modes are shown in
8-8
GCLK1
GCLK2
CLKOUT
(EBDF = 00)
GCLK1_50
(EBDF = 01)
GCLK2_50
(EBDF = 01)
CLKOUT
(EBDF = 01)
T1
T2
T3
T4
GCLK1_50
(EBDF = 00)
GCLK2_50
(EBDF = 00)
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 8-4. MPC561/MPC563 Clocks
Table
8-1. MODCK1 specifies
Freescale Semiconductor
Figure
8-7.