MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1101

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

A.2.13
In order to commence the execution of the compressed code, the DECRAM and the class information (in
the DCCR registers) must be programmed. The data to be programmed is supplied by the compressor tool
and the vocabulary generator. There are two initialization scenarios:
Freescale Semiconductor
1. Wake up in decompression off mode — If the chip wakes up with decompression disabled, the
2. Wake up in decompression on mode — If the chip wakes up in decompression on mode, it has to
— The ICDU:
initialization routine can be executed at any time before entering decompression on mode. After
the compression environment is initialized, the operational mode would be changed to
decompression on.
process compressed instructions without the vocabularies and class parameters. Thus, all
instructions executed until the end of the initialization routine should be compressed in the global
bypass format. DECRAM loading is an essential part of this intialization routine. After DECRAM
loading, efficient compressed code may be used.
Compressed
Instructions
Memory
– Converts the COF address to a word-aligned physical address to access the memory
– Fetches the compressed instruction code from the memory, decompresses it and delivers
Compression Environment Initialization
non-compressed instruction code, together with the bit-aligned next instruction address, to
the RCPU.
COF Word Aligned
Physical Address
Compressed
Instruction
Code
Figure A-12. Code Decompression Process
MPC561/MPC563 Reference Manual, Rev. 1.2
Classes (DCCR)
De
Registers
Vocabulary
compressor
ICDU
Compressed Space
“Next Instruction”
Bit-Aligned COF
Noncompressed
Instruction Code
Address
Address
MPC562/MPC564 Compression Features
Embedded
MPC500
CPU
A-13