MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 843

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

19.4.3
This register is accessible only when the TPU is in test mode; see
Registers.”
Freescale Semiconductor
1
T4 is one of the four basic timers (T1, T2, T3 & T4) used for microengine timing.
Bits
7:8
10
11
12
13
14
15
9
Development Support Status Register (DSSR)
Name
CCL
FRZ
BM
BP
BC
BH
BL
BT
FREEZE assertion response. The FRZ bits specify the TPU microengine response to the IMB3
FREEZE signal
00 Ignore freeze
01 Reserved
10 Freeze at end of current microcycle
11 Freeze at next time-slot boundary
Channel Conditions Latch. CCL controls the latching of channel conditions match recognition
latch (MRL) and transition detect latch (TDL) when the CHAN register is written. Refer to the TPU
Reference Manual (TPURM/AD) for further information.
0 Only the pin state condition of the new channel is latched as a result of the write CHAN register
1 Pin state, MRL, and TDL conditions of the new channel are latched as a result of a write CHAN
Breakpoint enable for microprogram counter (µPC)
0 Breakpoint not enabled
1 Break if µPC equals µPC breakpoint register
Channel breakpoint enable
0 Breakpoint not enabled
1 Break if CHAN register equals channel breakpoint register at beginning of state or when
Host service breakpoint enable
0 Breakpoint not enabled
1 Break if host service latch is asserted at beginning of state
Link service breakpoint enable
0 Breakpoint not enabled
1 Break if link service latch is asserted at beginning of state
MRL breakpoint enable
0 Breakpoint not enabled
1 Break if MRL is asserted at beginning of state
TDL breakpoint enable
0 Breakpoint not enabled
1 Break if TDL is asserted at beginning of state
microinstruction
register microinstruction
CHAN is changed through microcode
Table 19-8. DSCR Bit Descriptions (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
Description
Section 19.4.14, “Factory Test
Time Processor Unit 3
19-13