MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1086

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

IEEE 1149.1-Compliant Interface (JTAG)
25.1.3.4
The CLAMP instruction selects the single-bit bypass register as shown in
signals driven from system output pins is completely defined by the data previously shifted into the
boundary scan register (for example, using the SAMPLE/PRELOAD instruction).
25.1.4
The HI-Z instruction is provided as a manufacturer’s optional public instruction to prevent having to
backdrive the output pins during circuit-board testing. When HI-Z is invoked, all output drivers, including
the two-state drivers, are turned off (i.e., high impedance). The instruction selects the bypass register.
25.2
The control afforded by the output enable signals using the boundary scan register and the EXTEST
instruction requires a compatible circuit-board test environment to avoid device-destructive
configurations. The user must avoid situations in which the MPC561/MPC563 output drivers are enabled
into actively driven networks.
The MPC561/MPC563 features a low-power stop mode. The interaction of the scan chain interface with
low-power stop mode is as follows:
25.2.1
In non-scan chain operation, there are two constraints. First, the TCK input does not include an internal
pull-up resistor and should not be left unconnected to preclude mid-level inputs. The second constraint is
to ensure that the scan chain test logic is kept transparent to the system logic by forcing TAP into the
test-logic-reset controller state, using either of two methods. Connecting pin JCOMP to logic 0 (or one of
the reset pins), or TMS must be sampled as a logic one for five consecutive TCK rising edges. If then TMS
either remains unconnected or is connected to V
test-logic-reset state, regardless of the state of TCK.
25-32
1. The TAP controller must be in the test-logic-reset state to either enter or remain in the low-power
2. The TCK input is not blocked in low-power stop mode. To consume minimal power, the TCK input
3. The TMS pin includes an on-chip pull-up resistor. In low-power stop mode, this pin should remain
4. JCOMP must be low prior to PORESET assertion after low power mode exits otherwise an
stop mode. Leaving the TAP controller in the test-logic-reset state negates the ability to achieve
low-power, but does not otherwise affect device functionality.
should be externally connected to V
either unconnected or connected to VDD to achieve minimal power consumption. Note that for
proper reset of the scan chain test logic, the best approach is to pull JCOMP low at power-on reset
(PORESET).
unknown state will occur.
MPC561/MPC563 Restrictions
HI-Z
Non-Scan Chain Operation
CLAMP
MPC561/MPC563 Reference Manual, Rev. 1.2
DD
or ground.
DD
, then the TAP controller cannot leave the
Figure
25-5, and the state of all
Freescale Semiconductor