MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1174

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

TPU3 ROM Functions
D.10 Multichannel Pulse-Width Modulation (MCPWM)
MCPWM generates pulse-width modulated outputs with full 0 to 100% duty cycle range independent of
other TPU3 activity. This capability requires two TPU3 channels plus an external gate for one PWM. (A
simple one-channel PWM capability is supported by the QOM function.)
Multiple PWMs generated by MCPWM have two types of high time alignment: edge aligned and center
aligned. Edge-aligned mode uses n + 1 TPU3 channels for n PWMs, and center-aligned mode uses 2n + 1
channels. Center-aligned mode allows a user to define “dead time” so that two PWMs can be used to drive
an H-bridge without destructive current spikes. This feature is important for motor control applications.
See Freescale TPU Progamming Note Multichannel PWM TPU Function (MCPWM), (TPUPN05/D).
Figure D-12
through
Table D-17
shows the host interface areas for the MCPWM function in each mode.
MPC561/MPC563 Reference Manual, Rev. 1.2
D-22
Freescale Semiconductor