MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 460

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

U-Bus to IMB3 Bus Interface (UIMB)
The UIPEND register contains a status bit for each of the 32 interrupt levels. Each bit of the register is a
read-only status bit, reflecting the current state of the corresponding interrupt signal. For each of the 32
interrupt levels, a corresponding bit of the UIPEND register is set.
Figure 12-4
levels of interrupts.
12.5
Table 12-5
in this table is from the start of the block reserved for UIMB registers. As shown in
begins at offset 0x30 7F80 from the start of the MPC561/MPC563 internal memory map (the last 128-byte
sub-block of the UIMB interface memory map).
12-6
IMB3 LVL [0:7]
Access
IMBCLOCK
ILBS [0:1]
—
S
Programming Model
RESET
lists the registers used for configuring and testing the UIMB module. The address offset shown
shows how the eight interrupt lines are connected to the UIPEND register to represent 32
1
Software must poll this register to find out which of the levels 7 to 31 are
asserted.
0x30 7F84 — 0x30 7F8F Reserved
Figure 12-6
Base Address
0x30 7F80
Machine
Figure 12-6. Interrupt Synchronizer Block Diagram
State
shows the implementation of the interrupt synchronizer.
Table 12-5. UIMB Interface Register Map
MPC561/MPC563 Reference Manual, Rev. 1.2
4
UIMB Module Configuration Register (UMCR)
See
Table 12-6
NOTE
for bit descriptions.
LVL [8:31]
UIPEND
Register
LVL[0:7]
Register
LVL7
24
32
U-bus Interrupt Level[0:7]
7
OR
Figure
Freescale Semiconductor
U-bus
Data[0:31]
1-2, this block
8