MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 861

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

20.4.3
When a synchronous reset occurs, a bus master is allowed to complete the current access. Thus a write bus
cycle (byte, half word, or word) that is in progress when a synchronous reset occurs will be completed
without error. Once a write already in progress has been completed, further writes to the DPTRAM array
are inhibited.
If a reset is generated by an asynchronous reset such as the loss of clocks or software watchdog time-out,
the contents of the DPTRAM array are not guaranteed. (Refer to
MPC561/MPC563 reset sources, operation, control, and status.)
Reset will also reconfigure some of the fields and bits in the DPTRAM control registers to their default
reset state. See the description of the control registers to determine the effect of reset on these registers.
20.4.4
Setting DPTMCR[STOP] causes the module to enter its lowest power-consuming state. The DPTMCR can
still be written to allow the STOP control bit to be cleared.
In stop mode, the DPTRAM array cannot be read or written. All data in the array is retained The BIU
continues operating to allow the CPU to access the STOP bit in the DPTMCR. The system clock remains
stopped until the STOP bit is cleared or the DPTRAM module is reset.
The STOP bit is initialized to logical zero during reset. Only the STOP bit in the DPTMCR can be accessed
while the STOP bit is asserted. Accesses to other DPTRAM registers may result in unpredictable behavior.
The DPTRAM will not enter stop mode if one of the TPUs is in emulation mode using DPTRAM (i.e.,
TPUMCR[EMU] = 1)
20.4.5
The FREEZE line on the IMB3 has no effect on the DPTRAM module. When the freeze line is set, the
DPTRAM module will operate in its current mode of operation. If the DPTRAM module is not disabled,
(RAMDS = 0), it may be accessed via the IMB3. If the DPTRAM array is being used by the TPU3 in
emulation mode, the DPTRAM will still be able to be accessed by the TPU3 microengine.
20.4.6
To emulate TPU3 time functions, store in the RAM array the microinstructions required for all time
functions. Storing microinstructions must be done with the DPTRAM in its normal operating mode and
accessible from the IMB3. After the time functions are stored in the array, place one or both of the TPU3
units in emulation mode. The RAM array is then controlled by the TPU3 units and disconnected from the
IMB3.
To use the DPTRAM for microcode accesses, set the EMU bit in the corresponding TPU3 module
configuration register. Through the auxiliary buses, the TPU3 units can access word instructions
simultaneously at a rate of up to 56 MHz.
Freescale Semiconductor
Reset Operation
Stop Operation
Freeze Operation
TPU3 Emulation Mode Operation
MPC561/MPC563 Reference Manual, Rev. 1.2
Chapter 7,
“Reset” for a description of
Dual-Port TPU3 RAM (DPTRAM)
20-7