MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 284

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

System Configuration and Protection
6.2.2.4.7
The RTCAL is a 32-bit read/write register. When the value of the RTC is equal to the value programmed
in the alarm register, a maskable interrupt is generated.
The alarm interrupt will be generated as soon as there is a match between the ALARM field and the
corresponding bits in the RTC. The resolution of the alarm is 1 second. This register is locked after reset
by default. Unlocking is accomplished by writing 0x55CC AA33 to its associated key register. See
Section 8.8.3.2, “Keep-Alive Power Registers Lock
6.2.2.4.8
The PISCR contains the interrupt request level and the interrupt status bit. It also contains the controls for
the 16-bits to be loaded into a modulus counter. This register can be read or written at any time.
6-44
Reset
Field
Addr
Bits
9:12
PORESET
0:7
13
14
15
8
MSB
Field
Addr
0
Name
PIRQ
PITF
PTE
Real-Time Clock Alarm Register (RTCAL)
Periodic Interrupt Status and Control Register (PISCR)
PIE
PS
—
MSB
0
Figure 6-38. Periodic Interrupt Status and Control Register (PISCR)
1
Periodic interrupt request. These bits determine the interrupt priority level of the PIT. Refer to
Section 6.1.4, “Enhanced Interrupt
Periodic interrupt status. This bit is set if the PIT issues an interrupt. The PIT issues an interrupt
after the modulus counter counts to zero. PS can be negated by writing a one to it. A write of zero
has no affect.
Reserved
Periodic interrupt enable. If this bit is set, the time base generates an interrupt when the PS bit
is set.
PIT freeze. If this bit is set, the PIT stops while FREEZE is asserted.
Periodic timer enable
0 PIT stops counting and maintains current value
1 PIT continues to decrement
Figure 6-37. Real-Time Clock Alarm Register (RTCAL)
2
3
MPC561/MPC563 Reference Manual, Rev. 1.2
PIRQ
Table 6-20. PISCR Bit Descriptions
4
5
6
0000_0000_0000_0000
0x2F C22C
Unaffected
Controller” for interrupt level encoding.
Mechanism.”
ALARM
7
0x2F C240
Description
PS
8
9
10
—
11
12
PIE
Freescale Semiconductor
13
PITF
14
PTE
LSB
15
LSB
31