MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1058

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

IEEE 1149.1-Compliant Interface (JTAG)
25.1.2.1
The TAP controller is responsible for interpreting the sequence of logical values on the TMS signal. It is
a synchronous state machine that controls the operation of the JTAG logic. The state machine is shown in
Figure
rising edge of the TCK signal.
25.1.2.2
The MPC561/MPC563 scan chain implementation has a 427-bit (MPC563) or 423-bit (MPC561)
boundary scan register. This register contains bits for most device signals, clock pins and associated
control signals. The XTAL, EXTAL and XFC pins are associated with analog signals and are not included
in the boundary scan register. The PORESET, HRESET, and SRESET pins are also excluded from the
boundary scan register.
25-4
25-4. The value shown adjacent to each arc represents the value of the TMS signal sampled on the
TAP Controller
Boundary Scan Register
1
0
RUN-TEST/IDLE
TEST LOGIC
RESET
0
Figure 25-4. TAP Controller State Machine
MPC561/MPC563 Reference Manual, Rev. 1.2
1
1
0
1
SELECT-DR_SCAN
CAPTURE-DR
UPDATE-DR
PAUSE-DR
SHIFT-DR
EXIT1-DR
EXIT2-DR
0
0
1
0
1
1
0
0
0
0
1
1
0
1
SELECT-IR_SCAN
CAPTURE-IR
UPDATE-IR
PAUSE-IR
SHIFT-IR
EXIT1-IR
EXIT2-IR
0
0
1
0
1
1
0
0
0
Freescale Semiconductor
1
1