MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 80

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Suggested Reading
This section lists additional reading that provides background for the information in this manual as well as
general information about the PowerPC
this manual by providing in-depth functional descriptions of certain modules:
The following general documentation, available through Morgan-Kaufmann Publishers, 340 Pine Street,
Sixth Floor, San Francisco, CA, provides useful information about the PowerPC architecture:
Freescale documentation is available from the sources listed on the back cover of this manual. A brief
summary of available documentation is listed below:
Additional literature is published as new processors become available. For a current list of documentation,
refer to
Conventions and Nomenclature
This document uses the following notational conventions:
cleared/set
lxxx
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QSM (Queued Serial Module) Reference Manual (QSMRM/AD)
TPU (Time Processor Unit) documentation (TPULITPAK/D, including the TPURM/AD)
RCPU (RISC Central Processor Unit) Reference Manual (RCPURM/AD)
Nexus Standard Specification Rev 1.0 (IEEE-ISTO 5001-1999) available at:
http://www.nexus5001.org/
JTAG IEEE 1149.1 Specification
The PowerPC Architecture: A Specification for a New Family of RISC Processors, Second Edition,
by International Business Machines, Inc.
Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture
(MPCFPE32B/AD)—Describes resources defined by the PowerPC architecture.
Reference manuals—These books provide details about individual implementations and are
intended for use with the Programming Environments Manual.
Addenda/errata to reference manuals—Because some processors have follow-on parts, an
addendum is provided that describes the additional features and functionality changes and are
intended for use with the corresponding reference manuals.
Product Briefs—Each device has a product brief that provides an overview of its features. This
document is roughly the equivalent to the overview chapter (Chapter 1) of an implementation’s
reference manual.
The Programmer’s Reference Guide for the PowerPC Architecture (MPCPRG/D)—This concise
reference includes the register summary, exception vectors, and the PowerPC ISA instruction set.
Application notes—These short documents address specific design issues useful to programmers
and engineers working with Freescale processors.
http://www.motorola.com/semiconductors
When a bit takes the value zero, it is said to be cleared; when it takes a value of
one, it is said to be set.
MPC561/MPC563 Reference Manual, Rev. 1.2
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architecture. Also listed are documents that further complement
.
Freescale Semiconductor