MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 942

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Development Support
Not all exceptions are recognized when in debug mode. Breakpoints and watchpoints are not generated by
the hardware when in debug mode (regardless of the value of MSR[RI]). Upon entering debug mode
MSR[EE] is cleared by the hardware thus forcing the hardware to ignore external and decrementer
interrupts.
When the ecr_or signal is asserted the development station should investigate the exception cause register
(ECR) in order to find out the event that caused the exception.
Since the values in SRR0 and SRR1 do not change if an exception is recognized while already in debug
mode, they only change once when entering debug mode, saving them when entering debug mode is not
necessary.
23.3.1.6
The rfi instruction is used to exit from debug mode in order to return to the normal processor operation and
to negate the freeze indication. The development system may monitor the freeze status to make sure the
MPC561/MPC563 is out of debug mode. It is the responsibility of the software to read the exception cause
register (ECR) before performing the rfi. Failing to do so will force the CPU to immediately re-enter to
debug mode and to re-assert the freeze indication in case an asserted bit in the interrupt cause register
(ECR) has a corresponding enable bit set in the debug enable register (DER).
23.4
The development port provides a full duplex serial interface for communications between the internal
development support logic including debug mode and an external development tool.
The relationship of the development support logic to the rest of the CPU chip is shown in
development port support logic is shown as a separate block for clarity. It is implemented as part of the
SIU module.
23.4.1
The following development port pin functions are provided:
23-28
1. Development serial clock (DSCK)
2. Development serial data in (DSDI)
3. Development serial data out (DSDO)
Development Port
Development Port Pins
Exiting Debug Mode
Setting the MSR[EE] bit while in debug mode, (by the debug software), is
strictly forbidden. The reason for this restriction is that the external interrupt
event is a level signal, and since the CPU only reports exceptions while in
debug mode but do not treat them, the CPU does not clear the MSR[EE] bit
and, therefore, this event, if enabled, is recognized again every clock cycle.
MPC561/MPC563 Reference Manual, Rev. 1.2
WARNING
Freescale Semiconductor
Figure
23-5. The