MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 8

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

4.5.1
4.5.1.1
4.5.1.2
4.5.1.3
4.6
4.6.1
4.6.1.1
4.6.1.2
4.6.2
4.6.2.1
4.6.2.2
4.6.2.3
4.6.2.4
4.6.2.5
4.6.3
5.1
5.1.1
6.1
6.1.1
6.1.1.1
6.1.1.2
6.1.2
6.1.2.1
6.1.2.2
6.1.3
6.1.4
6.1.4.1
6.1.4.2
6.1.4.3
6.1.4.4
6.1.4.4.1
6.1.4.4.2
Freescale Semiconductor
Paragraph
Number
BBC Programming Model ............................................................................................ 4-17
Memory Map and Registers ............................................................................................ 5-2
System Configuration and Protection Features .............................................................. 6-3
BTB Operation .......................................................................................................... 4-14
Address Map ............................................................................................................. 4-17
BBC Register Descriptions ....................................................................................... 4-19
Decompressor Class Configuration Registers .......................................................... 4-25
USIU Special-Purpose Registers ................................................................................ 5-6
System Configuration ................................................................................................. 6-3
External Master Modes ............................................................................................... 6-4
USIU General-Purpose I/O ......................................................................................... 6-6
Enhanced Interrupt Controller .................................................................................... 6-8
BTB Invalidation .................................................................................................. 4-16
BTB Enabling/Disabling ...................................................................................... 4-16
BTB Inhibit Regions ............................................................................................. 4-16
BBC Special Purpose Registers (SPRs) ............................................................... 4-17
DECRAM and DCCR Block ................................................................................ 4-18
BBC Module Configuration Register (BBCMCR) ............................................... 4-19
Region Base Address Registers (MI_RBA[0:3]) ................................................. 4-21
Region Attribute Registers (MI_RA[0:3]) ............................................................ 4-22
Global Region Attribute Register (MI_GRA) ...................................................... 4-23
External Interrupt Relocation Table Base Address Register (EIBADR) .............. 4-25
USIU Pin Multiplexing ........................................................................................... 6-4
Arbitration Support ................................................................................................. 6-4
Operation in External Master Modes ...................................................................... 6-5
Address Decoding for External Accesses ............................................................... 6-6
Key Features ........................................................................................................... 6-8
Interrupt Configuration ........................................................................................... 6-8
Regular Interrupt Controller Operation (MPC555/MPC556-Compatible Mode) 6-10
Enhanced Interrupt Controller Operation ............................................................. 6-11
Lower Priority Request Masking ...................................................................... 6-14
Backward Compatibility with MPC555/MPC556 ............................................ 6-14
Unified System Interface Unit (USIU) Overview
System Configuration and Protection
MPC561/MPC563 Reference Manual, Rev. 1.2
Contents
Chapter 5
Chapter 6
Title
Number
Page
viii