MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 71

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

18-8
18-9
18-10
18-11
18-12
18-13
19-1
19-2
19-3
19-4
19-5
19-6
19-7
19-8
19-9
19-10
19-11
19-12
19-13
19-14
19-15
19-16
19-17
19-18
19-19
19-20
19-21
19-22
19-23
19-24
20-1
20-2
20-3
21-1
21-2
21-3
21-4
21-5
21-6
Freescale Semiconductor
Table
Number
SHORT_REG[SH_TCAN] Bit Settings ............................................................................... 18-20
SHORT_REG[SH_TPU] Bit Settings .................................................................................. 18-21
SHORT_CH_REG Bit Descriptions..................................................................................... 18-23
Examples of the SHORT_CH Bits ....................................................................................... 18-23
SCALE_TCLK Frequencies ................................................................................................. 18-24
SCALE_TCLK_REG Bit Descriptions ................................................................................ 18-24
TPU Memory Map.................................................................................................................. 19-1
Enhanced TCR1 Prescaler Divide Values .............................................................................. 19-6
TCR1 Prescaler Values ........................................................................................................... 19-6
TCR2 Counter Clock Source .................................................................................................. 19-7
TCR2 Prescaler Control.......................................................................................................... 19-8
TPU3 Register Map ................................................................................................................ 19-8
TPUMCR Bit Description .................................................................................................... 19-11
DSCR Bit Descriptions ......................................................................................................... 19-12
DSSR Bit Descriptions ......................................................................................................... 19-14
TICR Bit Description............................................................................................................ 19-15
CIER Bit Descriptions .......................................................................................................... 19-15
CFSRn Bit Descriptions........................................................................................................ 19-16
HSQRn Bit Descriptions....................................................................................................... 19-17
HSSRn Bit Descriptions ....................................................................................................... 19-18
CPRn Bit Description ........................................................................................................... 19-18
Channel Priorities ................................................................................................................. 19-18
CISR Bit Descriptions .......................................................................................................... 19-19
TPUMCR2 Bit Descriptions ................................................................................................. 19-19
Entry Table Bank Location................................................................................................... 19-20
System Clock Frequency/Minimum Guaranteed Detected Pulse......................................... 19-20
TPUMCR3 Bit Descriptions ................................................................................................. 19-21
SIUTST Bit Descriptions...................................................................................................... 19-22
Registers Used for Factory Test Only .................................................................................. 19-22
Parameter RAM Address Offset Map .................................................................................. 19-23
DPTRAM Register Map ......................................................................................................... 20-3
DPTMCR Bit Settings ............................................................................................................ 20-4
RAMBAR Bit Settings ........................................................................................................... 20-5
UC3F External Interface Signals ............................................................................................ 21-4
UC3F Register Programming Model ...................................................................................... 21-5
UC3FMCR Bit Descriptions................................................................................................... 21-6
UC3FMCRE Bit Descriptions ................................................................................................ 21-9
UC3FCTL Bit Descriptions .................................................................................................. 21-11
RCW Bit Descriptions .......................................................................................................... 21-17
MPC561/MPC563 Reference Manual, Rev. 1.2
Tables
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Number
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