MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1011

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Program trace synchronization messages provide the full address (without leading zeros) and ensure that
development tools fully synchronize with program trace regularly. Synchronization messages provide a
reference address for subsequent BTMs, in which only the unique portion of the program trace address is
transmitted.
It is also recommended that the USIU be programmed to ignore instruction show cycles so as to not impact
U-bus performance; set SIUMCR[NOSHOW]. Synchronization will only occur at changes in program
flow boundaries, and cannot be forced by the READI module. Synchronizations on errors, overflows, as
well as periodic synchronizations will not be deterministic to the nearest instruction, but to the next taken
change in program flow. The start of program trace (enabled via any means) will be also deferred to the
next change in program flow.
Program trace synchronization messages are of the following types:
Freescale Semiconductor
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Upon assertion of an event In (EVTI) signal. If the READI module is not disabled, an EVTI
assertion will cause the next BTM to be a synchronization message (provided the EC field is 0b00
in the DC register).
Upon occurrence of a watchpoint, the next BTM will be a synchronization message (provided
program trace is enabled).
Occurrence of queue overrun. A program trace overrun error occurs when a trace message cannot
be queued due to the queue being full. This causes the message queue to be flushed, and an error
message is placed as the first message in the queue. The error code within the error message will
indicate that program/data/ownership trace overrun has occurred. The next BTM will be a
synchronization message.
Sequential instruction count overflow. When the sequential instruction counter reaches its
maximum count (up to 256 sequential instructions may be executed), the next BTM will be a
program trace synchronization message.The sequential instruction counter is reset.
Upon entering or exiting code compression mode, the next BTM will be a synchronization
message.
The next change-of-flow instruction fetch following VSYNC will be a synchronization message.
Direct branch
Indirect branch
Direct branch with compressed code
Indirect branch with compressed code
Resource full
For program trace synchronization to work, the ICTRL register (refer to
Table
for all changes in the program flow (ISCTL field = 01) if the PTM bit is set
to 0. If the PTM bit is set to 1, ISCTL can be programmed to any value
except no show cycles (ISCTL field = 11).
23.6.11) must be programmed such that show cycle will be performed
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
READI Module
24-43