MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 856

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Dual-Port TPU3 RAM (DPTRAM)
20.2
20.3
The DPTRAM module consists of two separately addressable sections. The first is a set of
memory-mapped control and status registers used for configuration (DPTMCR, RAMBAR, MISRH,
MISRL, MISCNT) and testing (DPTTCR) of the DPTRAM array. The second section is the array itself.
All DPTRAM module control and status registers are located in supervisor data space. User read or write
attempts will result in a bus error.
When the TPU3 is using the RAM array for microcode control storage, none of these control registers has
any effect on the operation of the RAM array.
All addresses within the 64-byte control block will respond when accessed properly. Unimplemented
addresses will return zeros for read accesses. Likewise, unimplemented bits within registers will return
zero when read and will not be affected by write operations.
Table 20-1
internal system base address (see
Figure 1-3
20-2
•
•
•
•
— The DPTRAM array acts as a microcode storage for the TPU3 module. This provides a means
Includes built in check logic which scans the array contents and calculates the DPTRAM signature
IMB3 bus interface
Two TPU3 interface units
Byte, half-word, or word accessible
DPTRAM Configuration Block Diagram
Programming Model
to locate the DPTRAM control block in the MPC561/MPC563 address map.
of executing TPU3 code out of DPTRAM instead of TPU3 ROM.
shows the DPTRAM control and status registers. The addresses shown are offsets from the
RAM Mode
DPTRAM
MPC561/MPC563 Reference Manual, Rev. 1.2
TPU3
TPU3
Section 6.2.2.1.2, “Internal Memory Map Register
Figure 20-1. DPTRAM Configuration
TPU3 Emulation Mode
DPTRAM
TPU3
TPU3
Local Bus
Local Bus
Freescale Semiconductor
(IMMR)”). Refer to