MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 13

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

9.5.12
9.5.13
9.5.14
10.1
10.2
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
10.2.6
10.2.6.1
10.2.6.2
10.2.6.3
10.3
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
10.4
10.5
10.6
10.7
10.8
10.9
10.9.1
10.9.2
10.9.3
10.9.4
10.9.5
10.9.6
Freescale Semiconductor
Paragraph
Number
Overview ....................................................................................................................... 10-1
Memory Controller Architecture .................................................................................. 10-3
Chip-Select Timing ..................................................................................................... 10-10
Write and Byte Enable Signals ................................................................................... 10-24
Dual Mapping of the Internal Flash EEPROM Array ................................................ 10-24
Dual Mapping of an External Flash Region ............................................................... 10-26
Global (Boot) Chip-Select Operation ......................................................................... 10-27
Memory Controller External Master Support ............................................................. 10-28
Programming Model ................................................................................................... 10-31
Bus Operation in External Master Modes ................................................................. 9-49
Contention Resolution on External Bus .................................................................... 9-53
Show Cycle Transactions .......................................................................................... 9-55
Associated Registers ................................................................................................. 10-4
Port Size Configuration ............................................................................................ 10-4
Write-Protect Configuration ..................................................................................... 10-5
Address and Address Space Checking ...................................................................... 10-5
Burst Support ............................................................................................................ 10-5
Reduced Data Setup Time ........................................................................................ 10-6
Memory Devices Interface Example ...................................................................... 10-12
Peripheral Devices Interface Example .................................................................... 10-13
Relaxed Timing Examples ...................................................................................... 10-14
Extended Hold Time on Read Accesses ................................................................. 10-18
Summary of GPCM Timing Options ...................................................................... 10-22
General Memory Controller Programming Notes .................................................. 10-31
Memory Controller Status Registers (MSTAT) ..................................................... 10-32
Memory Controller Base Registers (BR0–BR3) .................................................... 10-32
Memory Controller Option Registers (OR0–OR3) ................................................ 10-34
Dual-Mapping Base Register (DMBR) .................................................................. 10-36
Dual-Mapping Option Register (DMOR) ............................................................... 10-37
Case 1: Normal Setup Time .................................................................................. 10-6
Case 2: Short Setup Time ..................................................................................... 10-7
Summary of Short Setup Time ............................................................................. 10-8
MPC561/MPC563 Reference Manual, Rev. 1.2
Memory Controller
Contents
Chapter 10
Title
Number
Page
xiii