MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 970

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

READI Module
24.1.1
The functional block diagram of the READI module is shown in
24-2
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Run-time access to on-chip memory map and MPC500 special purpose registers (SPRs) via the
READI read/write access protocol. This feature supports accesses for runtime internal visibility,
calibration constant acquisition and tuning, and external rapid prototyping for powertrain
automotive development systems.
Watchpoint messaging via the auxiliary port
Nine or 16 full-duplex auxiliary signal interface for medium and high visibility throughput
— One of two modes selected during reset: full port mode (FPM) and reduced port mode (RPM).
— Auxiliary output port
— Auxiliary input port
All features configurable and controllable via the auxiliary port
Security features for production environment
Support of existing RCPU development access protocol via the auxiliary port
READI module can be reset independent of system reset
Parametrics:
— Two bits are downloaded per clock in full port mode. For example, with input clock running at
— One bit is downloaded per clock in reduced port mode. For example, with input clock running
— Eight bits are uploaded per clock in full port mode. For example, with system clock running at
— Two bits are uploaded per clock in reduced port mode. For example, with system clock running
– FPM comprises 16 signals and RPM comprises nine signals
– One MCKO (message clock out) signal
– Two or eight MDO (message data out) signals
– One MSEO (message start/end out) signal
– One MCKI (message clock in) signal
– One or two MDI (message data in) signals
– One MSEI (message start/end in) signal
– One EVTI (event in) signal
– One RSTI (reset in) signal
28 MHz, this translates to a download rate of 56 Mbits/s.
at 28 MHz, this translates to a download rate of 28 Mbits/s.
56 MHz, this translates to a upload rate of 448 Mbits/s.
at 56 MHz, this translates to a upload rate of 112 Mbits/s.
Functional Block Diagram
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure
24-1.
Freescale Semiconductor