MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 166

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Central Processing Unit
The floating-point exception mode bits are interpreted as shown in
3.9.2
The DSISR, SPR 18, identifies the cause of data access and alignment exceptions.
For more information about bit settings, see
Section 3.15.4.6, “Alignment Exception
Data Protection Error Exception
3-22
Reset
Bits
Field
Addr
27
28
29
30
31
MSB
DAE/Source Instruction Service Register (DSISR)
0
DCMPEN Decompression On/Off. The reset value of this bit is (BBCMCR[EN_COMP] AND
Name
DR
LE
—
RI
1
01, 10, 11
2
FE[0:1]
Table 3-11. Machine State Register Bit Descriptions (continued)
00
3
Figure 3-12. DAE/Source Instruction Service Register (DSISR)
Data relocation.
0 Data address translation is off; the L2U DMPU does not check for address permission
1 Data address translation is on; the L2U DMPU checks for addressn permission attributes.
Reserved
BBCMCR[EXC_COMP]).
Note: This bit should not be set for the MPC561/MPC563.
0 The RCPU runs in normal operation mode.
1 The RCPU runs in compressed mode.
Note: MSR[DCMPEN] should not be changed by software by a direct MSR register write
Recoverable exception (for machine check and non-maskable breakpoint exceptions).
0 Machine state is not recoverable.
1 Machine state is recoverable.
Little-endian mode. This mode is not supported on MPC561/MPC563. This bit should be
cleared to 0 at all times.
0 The processor operates in big-endian mode during normal processing.
1 The processor operates in little-endian mode during normal processing.
4
attributes.
5
(MTMSR instruction). It can be changed only by the RFI instruction or by an exception.
6
floating-point assist error handler to be invoked.
handler is invoked precisely at the instruction that caused the enabled
exception.
Ignore exceptions mode. Floating-point exceptions do not cause the
Floating-point precise mode. The system floating-point assist error
Table 3-12. Floating-Point Exception Mode Bits
7
MPC561/MPC563 Reference Manual, Rev. 1.2
(0x1400).”
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
(0x00600),” and
Section 3.15.4.2, “Machine Check Exception
Unchanged
SPR 18
DSISR
Mode
Description
Section 3.15.4.15, “Implementation-Specific
Table
3-12.
Freescale Semiconductor
(0x0200),”
LSB
31