MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 444

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

L-Bus to U-Bus Interface (L2U)
11.6.1
The reservation protocol operates under the following assumptions:
11.6.2
The L2U is responsible for handling the effects of reservations on the L-bus and the U-bus. For the L-bus
and the U-bus, the L2U detects reservation losses.
The reservation logic in the L2U performs the following functions:
The unit for reservation is one word. A byte or half-word store request by another master will clear the
reservation flag.
A load-with-reservation request by the RPCU updates the reservation address related to a previous
load-with-reservation request and sets the reservation flag for the new location. A store-with-reservation
request by the RPCU clears the reservation flag. A store request by the RPCU does not clear the flag. A
store request by some other master to the reservation address clears the reservation flag.
If the storage reservation is lost, it is guaranteed that a store-with-reservation request by the RPCU will not
modify the storage.
The L2U does not start a store-with-reservation cycle on the U-bus if the reserved location on the U-bus
has been touched by another master. The L2U drives the reservation status back to the core.
When the reserved location in the CALRAM on the L-bus is touched by an alternate master, on the
following clock the L2U indicates to the RPCU that the reservation has been touched. On assertion of the
cancel-reservation signal, the RCPU clears the internal reservation bit. If an stwcx cycle has been issued
at the same time, the RCPU aborts the cycle. Software must check the CR0[EQ] bit to determine if the
stwcx instruction completed successfully.
Storage reservation is set regardless of the termination status (address or data phase) of the lwarx access.
Storage reservation is cleared regardless of the data phase termination status of the stwcx access if the
address phase is terminated normally.
11-8
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Each processor has at most 1 reservation flag
A lwarx instruction sets the reservation flag
Another lwarx instruction by same processor clears the reservation flag related to a previous lwarx
instruction and sets again the reservation flag
A stwcx instruction by the same processor clears the reservation flag
A store instruction by the same processor does not clear the reservation flag
Some other processor (or other mechanism) store to an address with an existing reservation clears
the reservation flag
In case the storage reservation is lost, it is guaranteed that stwcx will not modify the storage
Snoops accesses to all L-bus and U-bus slaves
Holds one reservation (address) for the core
Sets the reservation flag when the RPCU issues a load-with-reservation request
Reservation Protocol
L2U Reservation Support
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor