MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1000

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

READI Module
this rule are the development port access messages. See
Messaging,” for further details.
24.7.5.3
The following are examples of branch trace messages.
24.7.5.3.1
Table 24-23
uses a 4-bit output port.
Note that T0, I0, and A0 are the least significant bits where:
Tx = TCODE number (fixed)
Ix = Number of sequential instructions (variable)
Ax = Unique portion of the address (variable)
24-32
MSEx
illustrates an example of how the indirect branch public message is transmitted. The example
Branch Trace Message Examples
Example of Indirect Branch Message
During clock 7, the tool should ignore data on MDO signals.
Msb
TCODE (6 bits)
Figure 24-14. Transmission Sequence of Messages
1
Super Field
MPC561/MPC563 Reference Manual, Rev. 1.2
Lsb Msb
FIELD #1 (Var)
2
NOTE
Lsb Msb
Section 24.14.1, “RCPU Development Access
FIELD #2
3
Super Field
Lsb Msb
FIELD #3 (Var)
4
Freescale Semiconductor
Lsb