MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 813

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Peripheral Pin Multiplexing (PPM) Module
SYSCLK
PPM_TCLK
One Cycle
PPM_TSYNC
CH0
CH1
CH3
CH[K]
“1”
CH2
“1”
CH0
PPM_TX
CH0
CH[K]
CH1
CH3
CH0
CH2
PPM_RX
Shading of PPM_RX signifies value is unknown
Figure 18-6. One Transmit and Receive Cycle in SPI Mode
18.3.1.3
PPM Control Settings
As data is transferred through the PPM module it must be sampled at a rate which guarantees its validity.
This sample rate is a multiple of PPM_TCLK and is defined by the SAMP[0:2] field of the PPMPCR
register. For transmit operations, the sample rate is the rate at which TX_DATA receives data from the
internal modules. For receive operations, it is the rate at which the internal modules read RX_SHIFTER.
The register RX_DATA is updated from RX_SHIFTER on completed receive (PPM_TSYNC) cycles.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
18-7