MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1083

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

1.Bi-state outputs (Pin Function = O) such as mdo_2, and mdo_3, are incorporated with general I/O pads hard-wired to keep
2. Some input-only cells made with generic I/O pads are configured with “internal” control cells to keep them always in input mode,
3. This description allows ATPG tools to use a pin as a driver or receiver:
4. A modification to restrict ATPG tools to use a functional input-only pin as an input receiver only:.
5. The PORESET, HRESET, and SRESET pins are not part of the JTAG boundary scan chain. These pins are used in the reset
6. The XTAL, EXTAL, and XFC pins are associated with analog signals and are excluded from the boundary scan chain.
7. The READI module reset pin, rsti_b, (bsdl pin 517) is in the JTAG boundary scan chain, but must be kept at a “0” level during
8. Pad type naming conventions:
Freescale Semiconductor
output enable always on in system mode. The JTAG Control cell, indicated by the next lower bsdl bit in the chain, is configured
as an “internal” only cell to be held at a “1” value (always driving out) during JTAG testing.
such as epee, b0epee, and input pins that may be attached to analog references. Other input-only cells are configured as
bidirectional for JTAG testing, to give the board-level ATPG tools the flexability to use the pad as an input or output, depending
on the network of other devices that the pin is connected too. If it is desired to restrict these pins to only act as receivers during
JTAG mode, then these JTAG bsdl entries can be converted as shown in the example below:
configuration to enter JTAG. Board-level connections to them will not be testable with the EXTEST and CLAMP instructions.
They do respond to the HI-Z JTAG instruction for parametric testing purposes.6.
JTAG testing, (except for Hi-Z testing), due to system interactions. It is classified as a “linkage” pin, and its data and control
cells are configured to advise ATPG tools to drive a “0” value in during JTAG testing.
•26 V – 2.6 V
•5 V – 5 V
•s – slow
•f – fast
•h – high drive
•a – analog input
•i – input only
•d – has direct connection to the pad (may be used for module test)
BSDL
417
418
419
420
421
422
423
424
425
426
Bit
188
189
188
189
BC_2
BC_7
BC_2
BC_7
BC_2
BC_2
BC_2
BC_2
BC_2
BC_7
Type
Cell
BC_2
BC_7
BC_2
BC_4
IRQ3_B_KR_B_RETRY_B_
IRQ4_B_AT2_SGPIOC4
SGPIOC6_FRZ_PTR_B
Table 25-2. MPC563 Boundary Scan Bit Definition (continued)
Pin/Port Name
IWP0_VFLS0
IWP1_VFLS1
SGPIOC3
irq6_b_modck2
irq6_b_modck2
*
*
*
*
*
MPC561/MPC563 Reference Manual, Rev. 1.2
*
*
Function
controlr
controlr
controlr
internal
output2
internal
output2
controlr
internal
BSDL
bidir
bidir
bidir
input
bidir
Value
Safe
0
0
0
0
1
1
1
1
0
0
0
0
0
X
Contro
Cell
417
419
425
188
l
Disable
Value
0
0
0
0
IEEE 1149.1-Compliant Interface (JTAG)
Disabl
Result
Z
Z
Z
Z
e
Functio
I
I
Pin
IO
IO
IO
O
O
n
26v
26v
26v5vs
26v5vs
26v5vs
Type
Pad
26v
26v
25-29