MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 551

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

In stop mode:
If the STOP bit is clear, stop mode is disabled.
14.3.1.2
Freeze mode occurs when background debug mode is enabled in the USIU and a breakpoint is
encountered. This is indicated by the assertion of the internal FREEZE line on the IMB3. The FRZ bit in
the QADCMCR determines whether or not the QADC64E responds to an IMB3 internal FREEZE signal
assertion. Freeze is very useful when debugging an application.
When the internal FREEZE signal is asserted and the FRZ bit is set, the QADC64E finishes any conversion
in progress and then freezes.
Depending on when the FREEZE signal is asserted, there are three possible queue "freeze" scenarios:
During freeze mode, both the analog clock, QCLK, and periodic/interval timer are held in reset. When the
QADC64E enters the freeze mode while a queue is active, the current CCW location of the queue pointer
is saved.
During freeze, the analog clock, QCLK, is held in reset and the periodic/interval timer is held in reset.
External trigger events that occur during the freeze mode are not captured. The BIU remains active to
allow IMB3 access to all QADC64E registers and RAM. Although the QADC64E saves a pointer to the
next CCW in the current queue, the software can force the QADC64E to execute a different CCW by
writing new queue operating modes for normal operation. The QADC64E looks at the queue operating
modes, the current queue pointer, and any pending trigger events to decide which CCW to execute when
exiting freeze.
If the FRZ bit is clear, the internal FREEZE signal is ignored.
14.3.1.3
The LOCK and FLIP bits of the QADCMCR register control the operating mode of the QADC64E
modules. Out of reset, the QADC64E modules are in legacy mode (FLIP = 0) and the LOCK bit is clear,
Freescale Semiconductor
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BIU state machine and logic do not shut down
The CCW and Result RAM is not reset and is not accessible
The module configuration register (QADCMCR), the interrupt register (QADCINT), and the test
register (QADCTEST) are fully accessible and are not reset
The data direction register (DDRQA), port data register (PORTQA/PORTQB), and control register
0 (QACR0) are not reset and are read-only accessible
Control register 1 (QACR1), control register 2 (QACR2), and the status registers (QASR0 and
QASR1) are reset and are read-only accessible
In addition, the periodic/interval timer is held in reset during stop mode
When a queue is not executing, the QADC64E freezes immediately
When a queue is executing, the QADC64E completes the conversion in progress and then freezes
If, during the execution of the current conversion, the queue operating mode for the active queue
is changed, or a queue 2 abort occurs, the QADC64E freezes immediately
Freeze Mode
Switching Between Legacy and Enhanced Modes of Operation
MPC561/MPC563 Reference Manual, Rev. 1.2
QADC64E Enhanced Mode Operation
14-9