MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 951

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

instruction. Therefore, a valid data status will be output and the interrupt status will be saved for the next
transmission.
The sequencing error encoding indicates that the inputs from the external development tool are not what
the development port and/or the CPU was expecting. Two cases could cause this error:
This bus error will cause the CPU to signal that an interrupt (exception) occurred. Since a status of
sequencing error has a higher priority than exception, the port will report the sequencing error first, and
the CPU interrupt on the next transmission. The development port will ignore the command, instruction,
or data shifted in while the sequencing error or CPU interrupt is shifted out. The next transmission after
all error status is reported to the port should be a new instruction, trap enable or command (possibly the
one that was in progress when the sequencing error occurred).
The interrupt-occurred encoding is used to indicate that the CPU encountered an interrupt during the
execution of the previous instruction in debug mode. Interrupts may occur as the result of instruction
execution (such as unimplemented opcode or arithmetic error), because of a memory access fault, or from
an unmasked external interrupt. When an interrupt occurs the development port will ignore the command,
instruction, or data shifted in while the interrupt encoding was shifting out. The next transmission to the
port should be a new instruction, trap enable or debug port command.
Finally, the null encoding is used to indicate that no data has been transferred from the CPU to the
development port shift register.
23.4.6.11 Fast Download Procedure
The download procedure is used to download a block of data from the debug tool into system memory.
This procedure can be accomplished by repeating the following sequence of transactions from the
development tool to the debug port for the number of data words to be down loaded:
Freescale Semiconductor
1. The processor was trying to read instructions and there was data shifted into the development port,
2. The processor was trying to read data and there was instruction shifted into the development port.
or
The port will terminate the read cycle with a bus error.
INIT:
repeat: mfspr
until here
Save RX, RY
RY <- Memory Block address- 4
...
DATA word to be moved to memory
stwu
...
Restore RX,RY
Figure 23-12. Download Procedure Code Example
RX, DPDR
RX, 0x4(RY)
MPC561/MPC563 Reference Manual, Rev. 1.2
Development Support
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