MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 517

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Byte access to an even address of a QADC64E location is shown in the top illustration of
the case of write cycles, byte 1 of the register is not disturbed. In the case of a read cycle, the QADC64E
provides both byte 0 and byte 1.
Byte access to an odd address of a QADC64E location is shown in the center illustration of
In the case of write cycles, byte 0 of the register is not disturbed. In the case of read cycles, the QADC64E
provides both byte 0 and byte 1.
16-bit accesses to an even address read or write byte 0 and byte 1 as shown in the lowest illustration of
Figure
16-bit accesses to an odd address require two bus cycles; one byte of two different 16-bit QADC64E
locations is accessed. The first bus cycle is treated by the QADC64E as an 8-bit read or write of an odd
address. The second cycle is an 8-bit read or write of an even address. The QADC64E address space is
organized into 16-bit even address locations, so a 16-bit read or write of an odd address obtains or provides
the lower half of one QADC64E location, and the upper half of the following QADC64E location.
Freescale Semiconductor
13-26. The full 16 bits of data is written to and read from the QADC64E location with each access.
Intermodule Bus
Intermodule Bus
Intermodule Bus
QADC Location
QADC Location
QADC Location
8-bit Access of an Odd Address (ISIZ = 01, A0 = 1; OR ISIZ = 10, A0 = 1)
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 13-26. Bus Cycle Accesses
8-bit Access of an Even Address (ISIZ = 01, A0 = 0)
W
W
W
16-Bit Aligned Access (ISIZ = 10, A0 = 0)
Byte 0
Byte 0
Byte 0
Byte 0
BYTE 0
BYTE 0
R
R
R
W
W
W
Byte 1
Byte 1
Byte 1
Byte 1
BYTE 1
BYTE 1
R
R
R
QADC64E Legacy Mode Operation
QADC64E Bus CYC ACC
Figure
Figure
13-26. In
13-26.
13-53