MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1122

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Internal Memory Map
B-12
0x30 4150 –
0x30 415F
0x30 4160 –
0x30 416F
0x30 4170 –
0x30 417F
0x30 4180 –
0x30 418F
0x30 4190 –
0x30 419F
0x30 41A0 –
0x30 41AF
0x30 41B0 –
0x30 41BF
0x30 41C0 –
0x30 41CF
0x30 41D0 –
0x30 41DF
0x30 41E0 –
0x30 41EF
0x30 41F0 –
0x30 41FF
0x30 4400
0x30 4402
0x30 4404
0x30 4406
0x30 4408
0x30 440A
0x30 440C
0x30 440E
0x30 4410
0x30 4412
0x30 4414
0x30 4416
0x30 4418
0x30 441A
Address
1
Access
Table B-9. Time Processor Unit 3 A and B (TPU3 A and B) (continued)
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S
T
T
T
S
S
S
S
S
S
1
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
TPUMCR_B
HSQR0_B
HSQR1_B
HSRR0_B
HSRR1_B
CFSR0_B
CFSR1_B
CFSR2_B
CFSR3_B
DSCR_B
DSSR_B
Symbol
CIER_B
TICR_B
TCR_B
MPC561/MPC563 Reference Manual, Rev. 1.2
—
—
—
—
—
—
—
—
—
—
—
TPU3_A Channel 5 Parameter Registers.
See
TPU3_A Channel 6 Parameter Registers.
See
TPU3_A Channel 7 Parameter Registers.
See
TPU3_A Channel 8 Parameter Registers.
See
TPU3_A Channel 9 Parameter Registers.
See
TPU3_A Channel 10 Parameter Registers.
See
TPU3_A Channel 11 Parameter Registers.
See
TPU3_A Channel 11 Parameter Registers.
See
TPU3_A Channel 11 Parameter Registers.
See
TPU3_A Channel 14 Parameter Registers.
See
TPU3_A Channel 15 Parameter Registers.
See
TPU3_B Module Configuration Register
TPU3_B Test Configuration Register
TPU3_B Development Support Control Register
TPU3_B Development Support Status Register
TPU3_B Interrupt Configuration Register
TPU3_B Channel Interrupt Enable Register
TPU3_B Channel Function Selection Register 0
TPU3_B Channel Function Selection Register 1
TPU3_B Channel Function Selection Register 2
TPU3_B Channel Function Selection Register 3
TPU3_B Host Sequence Register 0
TPU3_B Host Sequence Register 1
TPU3_B Host Service Request Register 0
TPU3_B Host Service Request Register 1
Section 19.4.15
Section 19.4.15
Section 19.4.15
Section 19.4.15
Section 19.4.15
Section 19.4.15
Section 19.4.15
Section 19.4.15
Section 19.4.15
Section 19.4.15
Section 19.4.15
TPU3_B
Register
for more information.
for more information.
for more information.
for more information.
for more information.
for more information.
for more information.
for more information.
for more information.
for more information.
for more information.
Freescale Semiconductor
16, 32
16, 32
16, 32
16, 32
16, 32
16, 32
16, 32
16, 32
16, 32
16, 32
16, 32
16 only
Size
16
16
16
16
16
16
16
16
16
16
16
16
16
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Reset
S, M
S, M
S, M
S, M
S, M
S, M
S, M
S, M
S, M
S, M
S, M
S, M
S, M
S, M
—
—
—
—
—
—
—
—
—
—
—