MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 385

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

9.5.11
The MPC561/MPC563 bus architecture requires assertion of TA from an external device to signal that the
bus cycle is complete. TA is not asserted in the following cases:
External circuitry can provide TEA when no device responds by asserting TA within an appropriate period
of time after the MPC561/MPC563 initiates the bus cycle (it can be the internal bus monitor). This allows
the cycle to terminate and the processor to enter exception-processing for the error condition (each one of
the internal masters causes an internal interrupt under this situation). To properly control termination of a
bus cycle for a bus error, TEA must be asserted at the same time or before TA is asserted. TEA should be
negated before the second rising edge after it was sampled as asserted to avoid the detection of an error for
the next initiated bus cycle. TEA is an open drain pin that allows the “wired-or” of any different sources
of error generation.
9.5.11.1
When an external device asserts the RETRY signal during a bus cycle, the MPC561/MPC563 enters a
sequence in which it terminates the current transaction, relinquishes the ownership of the bus, and retries
the cycle using the same address, address attributes, and data (in the case of a write cycle).
Figure 9-32
termination of a transfer. As seen in this figure, in the case when the internal arbiter is enabled, the
MPC561/MPC563 negates BB and asserts BG in the clock cycle following the retry detection. This allows
any external master to gain bus ownership. In the next clock cycle, a normal arbitration procedure occurs
again. As shown in the figure, the external master did not use the bus, so the MPC561/MPC563 initiates a
new transfer with the same address and attributes as before.
In
arbiter. In this case, in the clock cycle after the RETRY signal is detected asserted, BR is negated together
with BB. One clock cycle later, the normal arbitration procedure occurs again.
Freescale Semiconductor
Figure
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•
The external device does not respond
Various other application-dependent errors occur
9-33, the same situation is shown except that the MPC561/MPC563 is working with an external
Bus Exception Control Cycles
illustrates the behavior of the MPC561/MPC563 when the RETRY signal is detected as a
Retrying a Bus Cycle
MPC561/MPC563 Reference Manual, Rev. 1.2
External Bus Interface
9-45