MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 557

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Table 14-10
Freescale Semiconductor
Bits
9:15
1:2
4:8
0
3
Prescaler
displays the bits in PRESCALER field which enable a range of QCLK frequencies
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
0001110
PRESCALER Prescaler Value. The PRESCALER value determines the QCLK frequency (f
[6:0]
EMUX
Name
TRG
—
—
f
SYSCLK
Div
10
11
12
13
14
15
Externally Multiplexed Mode. The EMUX bit allows the software to select the externally
multiplexed mode, which affects the interpretation of the channel numbers and forces the
MA0, MA1 and MA2 signals to be outputs.
0 Internally multiplexed, 16 possible channels
1 Externally multiplexed, up to 41 possible channels
See
Reserved
Trigger Assignment. The TRG bit allows the software to assign the ETRIG[2:1] signals to
queue 1 and queue 2.
0 ETRIG1 triggers queue 1, ETRIG2 triggers queue 2
1 ETRIG1 triggers queue 2, ETRIG2 triggers queue 1
Refer to
Reserved
to
clock frequency (f
(f
f
information on selecting a PRESCALER value.
2
2
3
4
5
6
7
8
9
SYSCLK
SYSCLK
Appendix F, “Electrical
Table 14-10. Prescaler f
Table 14-4
MPC561/MPC563 Reference Manual, Rev. 1.2
Prescaler
divisor. Refer to
Section 14.6.2, “External Trigger Input
). To keep f
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
0101010
0101011
0101100
0101101
0101110
Table 14-9. QACR0 Bit Descriptions
[6:0]
for more information.
QCLK
QCLK
f
SYSCLK
) values. f
Div
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
Section 14.4.5, “QADC64E Clock (QCLK)
Characteristics,” for more information on the QADC64E operating
within the specified range, the value of PRESCALER+1 is the
SYSCLK
QCLK
Prescaler
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
1001100
1001101
1001110
[6:0]
can range from 2-to-128 system clock cycles
Description
Divide-by Values
f
Signals.”
SYSCLK
Div
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
Prescaler
1100000
1100001
1100010
1100011
1100100
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
QADC64E Enhanced Mode Operation
[6:0]
Generation” for more
f
SYSCLK
100
101
102
103
104
105
106
107
108
109
110
111
Div
97
98
99
QCLK
). Refer
14-15