MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 462

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

U-Bus to IMB3 Bus Interface (UIMB)
12.5.2
The UTSTCREG register is used for factory testing only.
12.5.3
The UIPEND register is a read-only status register which reflects the state of the 32 interrupt levels. The
state of IRQ0 is shown in bit 0, the state of IRQ1 is shown in bit 1 and so on. This register is accessible
only in supervisor mode.
12-8
Bits
4:31
1:2
0
3
Test Control Register (UTSTCREG)
Pending Interrupt Request Register (UIPEND)
HSPEED
IRQMUX
Name
STOP
—
Stop enable.
0 Enable system clock for IMB3 bus
1 Disable IMB3 system clock
To avoid complications at restart and data corruption, system software must stop each slave on
the IMB3 before setting the STOP bit. Software must also ensure that all IMB3 interrupts have
been serviced before setting this bit.
Interrupt request multiplexing. These bits control the multiplexing of the 32 possible interrupt
requests onto the eight IMB3 interrupt request lines.
00 Disables the multiplexing scheme on the interrupt controller within this interface. What this
01 Enables the IMB3 IRQ control logic to perform a 2-to-1 multiplexing to allow transferring of 16
10 Enables the IMB3 IRQ control logic to perform a 3-to-1 multiplexing to allow transferring of 24
11 Enables the IMB3 IRQ control logic to perform a 4-to-1 multiplexing to allow transferring of 32
Half speed. The HSPEED bit controls the frequency at which the IMB3 runs with respect to the
U-bus. This is a modify-once bit. Software can write the reset value of this bit any number of
times. However, once logic 0 is written to this location, any attempt to rewrite this bit to a logic 1
will have no effect.
0 IMB3 frequency is the same as that of the U-bus
1 IMB3 frequency is one half that of the U-bus
Reserved
means is that the IMB3 IRQ [0:7] signals are non-multiplexed, only providing 8 [0:7] interrupt
request lines to the interrupt controller
[0:15] interrupt sources
[0:23]interrupt sources
[0:31] interrupt sources
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 12-6. UMCR Bit Descriptions
Description
Freescale Semiconductor