MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 877

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

21.2.2
The UC3F array is divided into eight blocks, 64 Kbytes in size, which may be independently erased. Two
blocks are host to a 16-Kbyte small block.
Seventeen bits of address are used to decode locations in the UC3F array. The read control logic in the
UC3F EEPROM module decodes the upper 14 bits of that address to determine if the desired data is
currently stored in one of the two read page buffers. If the data is already present in one of the two read
page buffers, a read operation is not completed to the UC3F array core, and 64 bits of data are transferred
from the appropriate read page buffer to the BIU. This type of array read access is an on-page read.
In the event that the read control logic determines that the desired data is not contained within one of the
read page buffers, a read access to the UC3F array core is completed and 32 bytes of data are transferred
from the array core. Only the addressed 64 bits of data will be transferred to the BIU. This type of array
read access is an off-page read. The BIU contains logic to implement the read page buffer update and
replacement scheme to transfer the 32 bytes of data into the appropriate read page buffer. If the read page
update and replacement scheme contains a random access mode that does not update the read page buffers,
the 32 bytes of data retrieved from the UC3F array core will not be transferred into either read page buffer.
The BIU is expected to contain page update logic for controlling the updating of the read page buffers.
Write accesses to the UC3F array have no effect except during program and erase operation.
21.2.3
The UC3F EEPROM module contains a special shadow row that is used to hold reset configuration data
and user data. See
The shadow row is accessed by setting UC3FMCR[SIE] = 1 and performing normal array accesses. Upon
transitioning SIE (a 1-to-0 or 0-to-1 transition), the read page match decode circuit is reset so that the next
array access is an off-page access.
The shadow row contains 512 bytes which are addressed for read accesses using the low order row and
read page addresses.
The shadow row is implemented in the lowest numbered block of the array. In the case of a UC3F array
configuration which also has a small block in the lowest numbered block of the array, the shadow row is
contained in the small block. If SBEN[0] = 1 in this array configuration, the shadow row is treated as part
of small block 0. SBPROTECT[0] and SBBLOCK[0] are used to control program and erase operation of
the shadow row. If SBEN[0] = 0 in this array configuration, the shadow row is treated as part of the host
block. The corresponding PROTECT and BLOCK bits are used to control program and erase operation of
the shadow row.
Freescale Semiconductor
UC3F EEPROM Array Addressing
UC3F EEPROM Shadow Row
A module cannot read its own shadow row. On the MPC563 the program
accessing the Flash shadow row must be executing from external memory
or from internal SRAM.
Figure
21-6.
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
CDR3 Flash (UC3F) EEPROM
21-15