MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 697

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

CAN 2.0B Controller Module
CAN Station 1
CAN Station 2
CAN Station n
MPC56x CAN System
CAN
ºº
Controller
(TouCAN)
CNTX0
CNRX0
Transceiver
Transceiver
Transceiver
Figure 16-2. Typical CAN Network
Each CAN station is connected physically to the CAN bus through an external transceiver. The transceiver
provides the transmit drive, waveshaping, and receive/compare functions required for communicating on
the CAN bus. It can also provide protection against damage to the TouCAN caused by a defective CAN
bus or a defective CAN station.
16.2.1
TouCAN Signal Sharing
The CNTX0 and CNRX0 signals of TouCAN_A and TouCAN_B are available at all times. The CNTX0
and CNRX0 signals of TouCAN_C are shared with MIOS14 GPIO signals (MPIO32B11, MPIO32B12)
or QSMCM SCI2 signals (TXD2/QGPO2, RXD2/QGPI2). The signal functions for these signals are
controlled by the PDMCR2[TCNC] register.
NOTE
Only one function can be enabled on a signal at a time.
16.3
TouCAN Architecture
The TouCAN module uses a flexible design that allows each of its 16 message buffers to be designated
either a transmit (Tx) buffer or a receive (Rx) buffer. In addition, to reduce the CPU overhead required for
message handling, each message buffer is assigned an interrupt flag bit to indicate that the transmission or
reception completed successfully.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
16-3