MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 934

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Development Support
economical interface (three pins) that allows the development system to operate in a lower frequency than
the frequency of the CPU. Note that it is also possible to debug the CPU using monitor debugger software,
for more information refer to
Section 23.5, “Software Monitor Debugger
Support.”
Debug mode is a state where the CPU fetches all instructions from the development port. In addition, when
in debug mode, data can be read from the development port and written to the development port. This
allows memory and registers to be read and modified by a development tool (emulator) connected to the
development port.
For protection purposes, two possible working modes are defined: debug mode enable and debug mode
disable. These working modes are selected only during reset. For more information refer to
Section 23.3.1.1, “Debug Mode Enable vs. Debug Mode
Disable.”
The user can work in debug mode starting from reset or the CPU can be programmed to enter debug mode
as a result of a predefined list of events. These events include all possible interrupts and exceptions in the
CPU system, including the internal breakpoints, together with two levels of development port requests
(masked and non-masked) and one peripheral breakpoint request that can be generated by any one of the
peripherals of the system (including internal and external modules). Each event can be programmed either
to be treated as a regular interrupt that causes the machine to branch to its interrupt vector, or to be treated
as a special interrupt that causes debug mode entry.
When in debug mode an rfi instruction will return the machine to its regular work mode. The debugger
tool should issue an isync instruction to the debug port prior to any other instructions when the CPU enters
debug mode after running code.
The relationship between the debug mode logic to the rest of the CPU chip is shown in
Figure
23-5.
MPC561/MPC563 Reference Manual, Rev. 1.2
23-20
Freescale Semiconductor