MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 931

• Manufacturer Part Number: MPC561MZP56
• Manufacturer: Freescale

Specifications of MPC561MZP56

• Cpu Family: MPC56x
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 56MHz
• Interface Type: QSPI/SCI/SPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 22
• Operating Supply Voltage (typ): 2.6/5V
• Operating Supply Voltage (max): 2.7/5.25V
• Operating Supply Voltage (min): 2.5/4.75V
• On-chip Adc: 2(32-chx10-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Lead Free Status / RoHS Status: Not Compliant

Note that when programming the load/store watchpoints to ignore L-addr events and L-data events, it does
not reduce the load/store watchpoints detection logic to be instruction watchpoint detection logic since the
instruction must be a load/store instruction for the load/store watchpoint event to trigger.
Freescale Semiconductor
Name
LWP0
LWP1
Description
Load/store
watchpoint
Load/store
watchpoint
Second
First
Table 23-8. Load/Store Watchpoints Programming Options
Instruction Events
IWP0, IWP1, IWP2,
IWP0, IWP1, IWP2,
MPC561/MPC563 Reference Manual, Rev. 1.2
ignore instruction
ignore instruction
Programming
Options
events
events
IWP3,
IWP3,
Programming Options
ignore L-addr events
Comparators (E | F)
Comparators (E | F)
ignore I-addr events
Comparators (E&F)
Comparators (E&F)
L-address Events
Comparator E
Comparator F
Comparator E
Comparator F
Programming Options
Comparators (G | H)
ignore L-data events
Comparators (G | H)
ignore L-data events
Comparators (G&H)
Comparators (G&H)
L-data Events
Comparator G
Comparator G
Comparator H
Comparator H
Development Support
23-17