MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 823

MPC561MZP56

Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet

Specifications of MPC561MZP56

Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant

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18.4.5
RX_DATA receives data from the RX_SHIFTER register. It is updated from RX_SHIFTER at the end of
a receive cycle (i.e., rising edge of PPM_TSYNC).
Freescale Semiconductor
SRESET
Field
Addr
Receive Data Register (RX_DATA)
MSB
0
CH15
Channel 0 is transmitted first.
Channel 0 is received first.
Channel Number
TX/RX_CONFIG
1
Table 18-6. Configuration Register (TX and RX) Channel Settings
Figure 18-17. Receive Configuration Register 2 (RX_CONFIG_2)
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
2
CH14
3
MPC561/MPC563 Reference Manual, Rev. 1.2
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO10
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
4
CH13
00
5
0000_0000_0000_0000
6
A_TPUCH10
A_TPUCH11
A_TPUCH12
A_TPUCH13
A_TPUCH14
A_TPUCH15
CH12
A_TPUCH0
A_TPUCH1
A_TPUCH2
A_TPUCH3
A_TPUCH4
A_TPUCH5
A_TPUCH6
A_TPUCH7
A_TPUCH8
A_TPUCH9
NOTE
0x30 5C10
01
7
Channel Values
8
CH11
B_TPUCH10
B_TPUCH11
B_TPUCH12
B_TPUCH13
B_TPUCH14
B_TPUCH15
B_TPUCH0
B_TPUCH1
B_TPUCH2
B_TPUCH3
B_TPUCH4
B_TPUCH5
B_TPUCH6
B_TPUCH7
B_TPUCH8
B_TPUCH9
9
10
10
Peripheral Pin Multiplexing (PPM) Module
CH10
11
MPWM16
MPWM17
MPWM18
MPWM19
MPWM20
MPWM21
MPWM0
MPWM1
MPWM2
MPWM3
MPWM4
MPWM5
MDA11
MDA12
MDA13
MDA14
12
11
CH9
13
14
CH8
LSB
15
18-17

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